In the design and packaging of semiconductor integrated circuits (ICs), there are several areas of concern. Moisture needs to be prevented from entering the circuits because: (1) moisture can be trapped in oxides and increase the dielectric constant thereof; (2) moisture can create trapped charge centers in gate oxides causing threshold voltage shifts in complementary metal-oxide-semiconductor (CMOS) transistors; (3) moisture can create interface states at the Si-gate oxide interface causing degradation in the transistor lifetime through increased hot-electron susceptibility; (4) moisture can cause corrosion of the metal interconnect, reducing the reliability of the IC; and (5) when trapped in Si-oxide, moisture can reduce the oxide mechanical strength and the oxide may become more prone to cracking due to tensile stress. Ionic contaminants can also cause damage to the IC as they can diffuse rapidly in silicon oxide. For instance, ionic contaminants can cause threshold voltage instability in CMOS transistors and alter the surface potential of the Si surface in the vicinity of the ionic contaminants. Dicing processes that separate adjacent IC dies from one another may also cause potential damage to the IC.
A seal ring has been used in the industry to protect the IC from moisture degradation, ionic contamination, and dicing processes, but improvement has been desirable. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Such scaling-down has produced a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as CMOS devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. However, problems arise when the high-k metal gate, gate last process causes chemical mechanical polishing (CMP) dishing in open areas, such as areas reserved for forming a seal ring around an integrated circuit die.
Accordingly, improved methods of semiconductor device fabrication and devices fabricated by such methods are desired.